//singed 32 bit   int_data_in
//32bit  float    float_data_out


//double
//1   sign
//11  exp  +1023
//52  base


//float 
//1  sign
//8  exp  +127
//23 base

module int2float(/*AUTOARG*/
   // Outputs
   float_data_out, out_valid,
   // Inputs
   clk, reset, int_data_in, in_valid
   );

input               clk               ;
input               reset             ;

input    [ 31:0]    int_data_in       ;
input               in_valid          ;
output   [ 31:0]    float_data_out   ;
output              out_valid         ;

////////////////////////////////////////////////////////////////////////////////
wire    [ 31:0]    abs_int_data      ;
reg     [ 31:0]    abs_int_data_reg  ;
reg                sign_int_data     ;
reg     [  5:0]    int_data_bit_cnt  ;  //signed
reg                in_valid_dly1     ;
reg                in_valid_dly2     ;
reg                out_valid         ;

reg     [ 31:0]    float_data_out        ;
reg     [ 31:0]    float_data_out_wire   ;

wire    [  7:0]    exp_cnt           ;


reg                 zero_flag   ;

assign    abs_int_data  = int_data_in[31]  ?     (int_data_in[31:0]==32'h8000_0000)  ?    (32'h7fff_ffff)  :   (~int_data_in[31:0]+1'd1)  
                                                                                                                               :   int_data_in[31:0]  ;
//assign    sign_int_data = int_data_in[31] ;

always @ (posedge clk )
begin
   sign_int_data <= int_data_in[31] ;
   abs_int_data_reg <= abs_int_data ;
   zero_flag  <=  (int_data_in=='d0);
end

//always @ (*)
always @ (posedge clk )
begin
   //if      (abs_int_data[62])  int_data_bit_cnt  <=  7'd62 ;
   //else if (abs_int_data[61])  int_data_bit_cnt  <=  7'd61 ;
   //else if (abs_int_data[60])  int_data_bit_cnt  <=  7'd60 ;
   //else if (abs_int_data[59])  int_data_bit_cnt  <=  7'd59 ;
   //else if (abs_int_data[58])  int_data_bit_cnt  <=  7'd58 ;
   //else if (abs_int_data[57])  int_data_bit_cnt  <=  7'd57 ;
   //else if (abs_int_data[56])  int_data_bit_cnt  <=  7'd56 ;
   //else if (abs_int_data[55])  int_data_bit_cnt  <=  7'd55 ;
   //else if (abs_int_data[54])  int_data_bit_cnt  <=  7'd54 ;
   //else if (abs_int_data[53])  int_data_bit_cnt  <=  7'd53 ;
   //else if (abs_int_data[52])  int_data_bit_cnt  <=  7'd52 ;
   //else if (abs_int_data[51])  int_data_bit_cnt  <=  7'd51 ;
   //else if (abs_int_data[50])  int_data_bit_cnt  <=  7'd50 ;
   //else if (abs_int_data[49])  int_data_bit_cnt  <=  7'd49 ;
   //else if (abs_int_data[48])  int_data_bit_cnt  <=  7'd48 ;
   //else if (abs_int_data[47])  int_data_bit_cnt  <=  7'd47 ;
   //else if (abs_int_data[46])  int_data_bit_cnt  <=  7'd46 ;
   //else if (abs_int_data[45])  int_data_bit_cnt  <=  7'd45 ;
   //else if (abs_int_data[44])  int_data_bit_cnt  <=  7'd44 ;
   //else if (abs_int_data[43])  int_data_bit_cnt  <=  7'd43 ;
   //else if (abs_int_data[42])  int_data_bit_cnt  <=  7'd42 ;
   //else if (abs_int_data[41])  int_data_bit_cnt  <=  7'd41 ;
   //else if (abs_int_data[40])  int_data_bit_cnt  <=  7'd40 ;
   //else if (abs_int_data[39])  int_data_bit_cnt  <=  7'd39 ;
   //else if (abs_int_data[38])  int_data_bit_cnt  <=  7'd38 ;
   //else if (abs_int_data[37])  int_data_bit_cnt  <=  7'd37 ;
   //else if (abs_int_data[36])  int_data_bit_cnt  <=  7'd36 ;
   //else if (abs_int_data[35])  int_data_bit_cnt  <=  7'd35 ;
   //else if (abs_int_data[34])  int_data_bit_cnt  <=  7'd34 ;
   //else if (abs_int_data[33])  int_data_bit_cnt  <=  7'd33 ;
   //else if (abs_int_data[32])  int_data_bit_cnt  <=  7'd32 ;
   //else if (abs_int_data[31])  int_data_bit_cnt  <=  7'd31 ;
   //else if (abs_int_data[30])  int_data_bit_cnt  <=  7'd30 ;

   if (abs_int_data[30])       int_data_bit_cnt  <=  6'd30 ;
   else if (abs_int_data[29])  int_data_bit_cnt  <=  6'd29 ;
   else if (abs_int_data[28])  int_data_bit_cnt  <=  6'd28 ;
   else if (abs_int_data[27])  int_data_bit_cnt  <=  6'd27 ;
   else if (abs_int_data[26])  int_data_bit_cnt  <=  6'd26 ;
   else if (abs_int_data[25])  int_data_bit_cnt  <=  6'd25 ;
   else if (abs_int_data[24])  int_data_bit_cnt  <=  6'd24 ;
   else if (abs_int_data[23])  int_data_bit_cnt  <=  6'd23 ;
   else if (abs_int_data[22])  int_data_bit_cnt  <=  6'd22 ;
   else if (abs_int_data[21])  int_data_bit_cnt  <=  6'd21 ;
   else if (abs_int_data[20])  int_data_bit_cnt  <=  6'd20 ;
   else if (abs_int_data[19])  int_data_bit_cnt  <=  6'd19 ;
   else if (abs_int_data[18])  int_data_bit_cnt  <=  6'd18 ;
   else if (abs_int_data[17])  int_data_bit_cnt  <=  6'd17 ;
   else if (abs_int_data[16])  int_data_bit_cnt  <=  6'd16 ;
   else if (abs_int_data[15])  int_data_bit_cnt  <=  6'd15 ;
   else if (abs_int_data[14])  int_data_bit_cnt  <=  6'd14 ;
   else if (abs_int_data[13])  int_data_bit_cnt  <=  6'd13 ;
   else if (abs_int_data[12])  int_data_bit_cnt  <=  6'd12 ;
   else if (abs_int_data[11])  int_data_bit_cnt  <=  6'd11 ;
   else if (abs_int_data[10])  int_data_bit_cnt  <=  6'd10 ;
   else if (abs_int_data[ 9])  int_data_bit_cnt  <=  6'd9  ;
   else if (abs_int_data[ 8])  int_data_bit_cnt  <=  6'd8  ;
   else if (abs_int_data[ 7])  int_data_bit_cnt  <=  6'd7  ;
   else if (abs_int_data[ 6])  int_data_bit_cnt  <=  6'd6  ;
   else if (abs_int_data[ 5])  int_data_bit_cnt  <=  6'd5  ;
   else if (abs_int_data[ 4])  int_data_bit_cnt  <=  6'd4  ;
   else if (abs_int_data[ 3])  int_data_bit_cnt  <=  6'd3  ;
   else if (abs_int_data[ 2])  int_data_bit_cnt  <=  6'd2  ;
   else if (abs_int_data[ 1])  int_data_bit_cnt  <=  6'd1  ;
   else if (abs_int_data[ 0])  int_data_bit_cnt  <=  6'd0  ;
   else                        int_data_bit_cnt  <=  6'h20 ;
end

//assign  exp_cnt = (int_data_bit_cnt[5])  ?   8'd254  :  (8'd255+int_data_bit_cnt[5:0])  ;
//  (-1 or cnt) + 255
assign  exp_cnt = (int_data_bit_cnt[5])  ?   8'd126  :  (8'd127+int_data_bit_cnt[5:0])  ;

//always @ (*)
always@ ( posedge clk)
begin
   //if      (abs_int_data_reg[62]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[61:10]     }      ;   // notice !!!!no round here!!!    
   //else if (abs_int_data_reg[61]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[60: 9]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[60]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[59: 8]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[59]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[58: 7]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[58]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[57: 6]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[57]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[56: 5]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[56]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[55: 4]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[55]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[54: 3]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[54]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[53: 2]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[53]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[52: 1]     }      ;   // notice !!!!no round here!!!
   //else if (abs_int_data_reg[52]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[51: 0]     }      ;   
   //else if (abs_int_data_reg[51]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[50: 0], 1'd0}    ;
   //else if (abs_int_data_reg[50]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[49: 0], 2'd0}    ;
   //else if (abs_int_data_reg[49]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[48: 0], 3'd0}    ;
   //else if (abs_int_data_reg[48]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[47: 0], 4'd0}    ;
   //else if (abs_int_data_reg[47]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[46: 0], 5'd0}    ;
   //else if (abs_int_data_reg[46]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[45: 0], 6'd0}    ;
   //else if (abs_int_data_reg[45]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[44: 0], 7'd0}    ;
   //else if (abs_int_data_reg[44]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[43: 0], 8'd0}    ;
   //else if (abs_int_data_reg[43]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[42: 0], 9'd0}    ;
   //else if (abs_int_data_reg[42]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[41: 0],10'd0}    ;
   //else if (abs_int_data_reg[41]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[40: 0],11'd0}    ;
   //else if (abs_int_data_reg[40]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[39: 0],12'd0}    ;
   //else if (abs_int_data_reg[39]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[38: 0],13'd0}    ;
   //else if (abs_int_data_reg[38]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[37: 0],14'd0}    ;
   //else if (abs_int_data_reg[37]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[36: 0],15'd0}    ;
   //else if (abs_int_data_reg[36]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[35: 0],16'd0}    ;
   //else if (abs_int_data_reg[35]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[34: 0],17'd0}    ;
   //else if (abs_int_data_reg[34]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[33: 0],18'd0}    ;
   //else if (abs_int_data_reg[33]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[32: 0],19'd0}    ;
   //else if (abs_int_data_reg[32]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[31: 0],20'd0}    ;
   //else if (abs_int_data_reg[31]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[30: 0],21'd0}    ;
   //else if (abs_int_data_reg[30]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[29: 0],22'd0}    ;
   //base is  23 bit 
   if      (abs_int_data_reg[30]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[29: 7]      }    ;
   else if (abs_int_data_reg[29]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[28: 6]      }    ;
   else if (abs_int_data_reg[28]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[27: 5]      }    ;
   else if (abs_int_data_reg[27]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[26: 4]      }    ;
   else if (abs_int_data_reg[26]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[25: 3]      }    ;
   else if (abs_int_data_reg[25]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[24: 2]      }    ;
   else if (abs_int_data_reg[24]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[23: 1]      }    ;
   else if (abs_int_data_reg[23]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[22: 0]      }    ;
   else if (abs_int_data_reg[22]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[21: 0], 1'd0}    ;
   else if (abs_int_data_reg[21]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[20: 0], 2'd0}    ;
   else if (abs_int_data_reg[20]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[19: 0], 3'd0}    ;
   else if (abs_int_data_reg[19]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[18: 0], 4'd0}    ;
   else if (abs_int_data_reg[18]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[17: 0], 5'd0}    ;
   else if (abs_int_data_reg[17]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[16: 0], 6'd0}    ;
   else if (abs_int_data_reg[16]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[15: 0], 7'd0}    ;
   else if (abs_int_data_reg[15]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[14: 0], 8'd0}    ;
   else if (abs_int_data_reg[14]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[13: 0], 9'd0}    ;
   else if (abs_int_data_reg[13]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[12: 0],10'd0}    ;
   else if (abs_int_data_reg[12]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[11: 0],11'd0}    ;
   else if (abs_int_data_reg[11]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[10: 0],12'd0}    ;
   else if (abs_int_data_reg[10]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 9: 0],13'd0}    ;
   else if (abs_int_data_reg[ 9]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 8: 0],14'd0}    ;
   else if (abs_int_data_reg[ 8]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 7: 0],15'd0}    ;
   else if (abs_int_data_reg[ 7]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 6: 0],16'd0}    ;
   else if (abs_int_data_reg[ 6]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 5: 0],17'd0}    ;
   else if (abs_int_data_reg[ 5]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 4: 0],18'd0}    ;
   else if (abs_int_data_reg[ 4]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 3: 0],19'd0}    ;
   else if (abs_int_data_reg[ 3]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 2: 0],20'd0}    ;
   else if (abs_int_data_reg[ 2]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[ 1: 0],21'd0}    ;
   else if (abs_int_data_reg[ 1]) float_data_out_wire <= {sign_int_data,exp_cnt,abs_int_data_reg[    0],22'd0}    ;
   else if (abs_int_data_reg[ 0]) float_data_out_wire <= {sign_int_data,exp_cnt,                        23'd0}    ;
   else                           float_data_out_wire <= {sign_int_data,exp_cnt,                        23'd0}    ;
end                          

reg    [1:0]    zero_flag_dly ;

always@ (  posedge clk)
begin
     float_data_out         <=   zero_flag_dly[0]   ?    'd0   :    (float_data_out_wire[31]&&(float_data_out_wire[30:0]==32'd0))  ?  'd0  :   float_data_out_wire             ;
end

always@ (  posedge clk)
begin
     out_valid          <= reset  ?  1'd0  :   in_valid_dly2   ;
     in_valid_dly1      <= reset  ?  1'd0  :   in_valid       ;
     in_valid_dly2      <= reset  ?  1'd0  :   in_valid_dly1  ;
     zero_flag_dly      <= reset  ?  2'd0  :   {zero_flag_dly[0],zero_flag}   ;
 
end


endmodule                    

